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vivado2020在编译过程中报错总结

2021/1/13 20:12:57 文章标签: 测试文章如有侵权请发送至邮箱809451989@qq.com投诉后文章立即删除

目前在使用vivado2020.2和vivado2018.2调试FPGA,由于以前没有使用过vivado,在调试过程中遇到不少问题, 为防止以后再遇到类似问题浪费时间去解决这些本不该出现的错误,在此对这些常见错误进行总结: 1、在IMPLEMENTATI…

        目前在使用vivado2020.2和vivado2018.2调试FPGA,由于以前没有使用过vivado,在调试过程中遇到不少问题,

为防止以后再遇到类似问题浪费时间去解决这些本不该出现的错误,在此对这些常见错误进行总结:

        1、在IMPLEMENTATION过程中,出现Place Design error:

        [Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.
        [Common 17-69] Command failed: Placer could not place all instances
        这个问题是由于顶层文件没有输出接口信号导致的,只需要添加一个测试接口信号,就可以消除报错。

        2、在IMPLEMENTATION--Write Bitstream过程中,出现Pin Planning error: 

  • [DRC NSTD-1] Unspecified I/O Standard: 1 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_rst_n.
  • [DRC UCIO-1] Unconstrained Logical Port: 1 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: sys_rst_n.
  • [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

      这个问题的解决办法是对输出信号接口未约束的部分添加unused_pin.tcl文件,具体代码如下:

      set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
      set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
      set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]    

      将这部分代码保存为unused_pin.tcl文件,然后添加进工程即可:

      将文件保存到和.xdc同目录下,然后在Project manager——Settings中设置如下,重新编译即可。

      


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